The invention relates generally to the manufacture of integrated circuits and, more particularly, to the isolation of a vertical gate contact of a transistor structure.
Semiconductor memories, such as dynamic random access memories (DRAMs), typically include memory cells. These memory cells include storage nodes which are formed within deep trenches etched into substrates of the semiconductor memory chip. The storage nodes are accessed using a transistor which allows a charge to be stored in the storage node or retrieves a charge from the storage node, depending on the desired action (i.e., read or write). The storage node must be sufficiently electrically isolated from the gate conductor.
One way to ensure sufficient electrical isolation of the storage node is to provide a top trench oxide layer over the storage node. The storage nodes typically include polysilicon material that partially fills the deep trench. During fabrication, the polysilicon leaves a recess remaining at the top of the trench. An oxide (silicon dioxide) is deposited over the surface of the semiconductor device. During the oxide deposition, oxide is formed over the polysilicon in the trench. Other portions of the deposited oxide are removed by planarizing the surface of the semiconductor device and by recessing the oxide to leave a 30-50 nm oxide layer at the bottom of the recess. This oxide layer is referred to as a trench top oxide or isolation.
In the case where vertical transistors are fabricated on the memory device, a buried strap portion of the storage node (i.e., the portion directly below the top trench oxide) must outdiffuse to connect to a vertical transistor channel which extends along a gate conductor in the deep trench above the top trench oxide. In this way, when the vertical transistor conducts, a connection is made between the storage node and a bit line. The channel must be electrically isolated from the gate conductor (GC). Therefore, an insulating layer is provided, typically an oxide layer formed by oxidizing single crystalline silicon within the deep trench and the channel.
In the vertical array device DRAM process, the GC etch is required to remove excess vertical gate material to avoid shorts between the word line and the bit line. FIG. 1 illustrates the problem with residues in the xe2x80x9ctraditionalxe2x80x9d vertical gate process. The GC etch is required to etch excess pedestal material out of a box that is formed by the edge of GC 130 (isolated from active area 150 by array top oxide 180), trench top nitride spacer 160 and the two (2) sides bordering on the isolation trench (IT) which is both in front of and behind the plane of FIG. 1. The weakest point is tip 170 of vertical gate pedestal 120, but includes GC 130 and vertical gate 110 because the conductive gate material can later short. Tip 170 is the weakest point because it has the least amount of SiN 140 on top of it. In this scenario, the bit line contact (not shown) is likely to short to vertical gate 110 because the GC etch may leave polysilicon residues on the sidewalls of the box. The residues can cause shorts to the bit line contact (CB). The bit line contacts will be etched later, to the left and right of the GC 130 line. This etch needs to contact active areas 150, which are silicon (Si). It is an oxide etch that is selective to SiN. Therefore, it is important to have sufficient SiN 140 over all exposed material of GC 130, vertical gate pedestal 120 and vertical gate 110. This prevents the bit line contact (CB) etch from penetrating through to GC 130 and causing a short. Even more critical are the sides of vertical gate pedestal 120 bordering on the IT because these sidewalls are more vertical or even re-entrant and therefore more prone to GC residues after the highly anisotropic GC etch.
It is therefore desirable to enable an easy post GC etch treatment that can remove vertical GC residues without affecting the support devices, while ensuring a robust GC to vertical gate contact in all alignment scenarios.
The present invention provides an easy post GC etch treatment that can remove vertical GC residues without affecting the support devices while ensuring a robust GC to vertical gate contact in all alignment scenarios. The conductive vertical gate contact of the present invention, in conjunction with any deep trench top isolation approach, allows for an aggressive post GC etch treatment to avoid gate to bit line shorts without compromising the contact between the GC and the vertical gate.